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| ZL30123 SONET/SDH Low Jitter Line Card Synchronizer Data Sheet May 2006 A full Design Manual is available to qualified customers. To register, please send an email to TimingandSync@Zarlink.com. Ordering Information ZL30123GGG 100 Pin CABGA Trays ZL30123GGG2 100 Pin CABGA* Trays *Pb Free Tin/Silver/Copper -40oC to +85oC * DPLL2 provides a comprehensive set of features for generating derived output clocks and other general purpose clocks Provides 8 reference inputs which support clock frequencies with any multiples of 8 kHz up to 77.76 MHz in addition to 2 kHz Provides 3 sync inputs for output frame pulse alignment Generates several styles of output frame pulses with selectable pulse width, polarity, and frequency Configurable input to output delay, and output to output phase alignment Flexible input reference monitoring automatically disqualifies references based on frequency and phase irregularities Supports IEEE 1149.1 JTAG Boundary Scan Features * Synchronizes with standard telecom system references and synthesizes a wide variety of protected telecom line interface clocks that are compliant with Telcordia GR-253-CORE and ITU-T G.813 Internal APLL provides standard output clock frequencies up to 622.08 MHz with jitter < 3 ps RMS suitable for GR-253-CORE OC-12 and G.813 STM-16 interfaces Programmable output synthesizers (P0, P1) generate clock frequencies from any multiple of 8 kHz up to 77.76 MHz in addition to 2 kHz Provides two DPLLs which are independently configurable through a serial peripheral interface DPLL1 provides all the features necessary for generating SONET/SDH compliant clocks including automatic hitless reference switching, automatic mode selection (locked, free-run, holdover), and selectable loop bandwidth * * * * * * * * * * trst_b tck tdi tms tdo dpll2_ref dpll1_hs_en dpll1_lock dpll1_holdover diff0_en diff1_en osco osci Master Clock IEEE 1449.1 JTAG ref DPLL2 P0 Synthesizer P1 Synthesizer p0_clk0 p0_clk1 p0_fp0 p0_fp1 p1_clk0 p1_clk1 diff0 diff1 ref0 ref1 ref2 ref3 ref4 ref5 ref6 ref7 sync0 sync1 sync2 ref7:0 ref DPLL1 sync2:0 Reference Monitors ref_&_sync_status sync fb_clk/fp SONET/SDH APLL sdh_clk0 sdh_clk1 sdh_fp0 sdh_fp1 fb_clk Feedback Synthesizer int_b SPI Interface Controller & State Machine sck si so cs_b rst_b dpll1_mod_sel1:0 sdh_filter filter_ref0 filter_ref1 Figure 1 - Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2006, Zarlink Semiconductor Inc. All Rights Reserved. ZL30123 Applications * * * * * * AMCs for AdvancedTCATM and MicroTCA Systems Multi-Service Edge Switches or Routers DSLAM Line Cards WAN Line Cards RNC/Mobile Switching Center Line Cards ADM Line Cards Data Sheet 2 Zarlink Semiconductor Inc. ZL30123 Table of Contents Data Sheet 1.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 DPLL Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2 DPLL Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.3 Ref and Sync Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.4 Ref and Sync Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.5 Output Clocks and Frame Pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.6 Configurable Input-to-Output and Output-to-Output Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.0 Software Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.0 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3 Zarlink Semiconductor Inc. ZL30123 List of Figures Data Sheet Figure 1 - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Automatic Mode State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 3 - Reference and Sync Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 4 - Output Frame Pulse Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 5 - Behaviour of the Guard Soak Timer during CFM or SCM Failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 6 - Output Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 7 - Phase Delay Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 Zarlink Semiconductor Inc. ZL30123 List of Tables Data Sheet Table 1 - DPLL1 and DPLL2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 2 - Set of Pre-Defined Auto-Detect Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 3 - Set of Pre-Defined Auto-Detect Sync Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 4 - Output Clock and Frame Pulse Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 5 - Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 Zarlink Semiconductor Inc. ZL30123 Pin Description Pin # Name I/O Type Description Data Sheet Input Reference C1 B2 A3 C3 B3 B4 C4 A4 B1 A1 A2 ref0 ref1 ref2 ref3 ref4 ref5 ref6 ref7 sync0 sync1 sync2 Id Input References (LVCMOS, Schmitt Trigger). These are input references available to both DPLL1 and DPLL2 for synchronizing output clocks. All eight input references can be automatically or manually selected using software registers. These pins are internally pulled down to Vss. Id Frame Pulse Synchronization References (LVCMOS, Schmitt Trigger). These are the frame pulse synchronization inputs associated with input references 0, 1 and 2. These inputs accept frame pulses in a clock format (50% duty cycle) or a basic frame pulse format with minimum pulse width of 5 ns. These pins are internally pulled down to Vss. Output Clocks and Frame Pulses D10 sdh_clk0 O SONET/SDH Output Clock 0 (LVCMOS). This output can be configured to provide any one of the SONET/SDH clock outputs up to 77.76 MHz. The default frequency for this output is 77.76 MHz. SONET/SDH Output Clock 1 (LVCMOS). This output can be configured to provide any one of the SONET/SDH clock outputs up to 77.76 MHz. The default frequency for this output is 19.44 MHz. SONET/SDH Output Frame Pulse 0 (LVCMOS). This output can be configured to provide virtually any style of output frame pulse synchronized with an associated SONET/SDH family output clock. The default frequency for this frame pulse output is 8 kHz. SONET/SDH Output Frame Pulse 1 (LVCMOS). This output can be configured to provide virtually any style of output frame pulse synchronized with an associated SONET/SDH family output clock. The default frequency for this frame pulse output is 2 kHz. Programmable Synthesizer 0 - Output Clock 0 (LVCMOS). This output can be configured to provide any frequency with a multiple of 8 kHz up to 77.76 MHz in addition to 2 kHz. The default frequency for this output is 2.048 MHz. Programmable Synthesizer 0 - Output Clock 1 (LVCMOS). This is a programmable clock output configurable as a multiple or division of the p0_clk0 frequency within the range of 2 kHz to 77.76 MHz. The default frequency for this output is 8.192 MHz. Programmable Synthesizer 0 - Output Frame Pulse 0 (LVCMOS). This output can be configured to provide virtually any style of output frame pulse associated with the p0 clocks. The default frequency for this frame pulse output is 8 kHz. Programmable Synthesizer 0 - Output Frame Pulse 1 (LVCMOS). This output can be configured to provide virtually any style of output frame pulse associated with the p0 clocks. The default frequency for this frame pulse output is 8 kHz. G10 sdh_clk1 O E10 sdh_fp0 O F10 sdh_fp1 O K9 p0_clk0 O K7 p0_clk1 O K8 p0_fp0 O J7 p0_fp1 O 6 Zarlink Semiconductor Inc. ZL30123 Pin # J10 Name p1_clk0 I/O Type O Description Data Sheet Programmable Synthesizer 1 - Output Clock 0 (LVCMOS). This output can be configured to provide any frequency with a multiple of 8 kHz up to 77.76 MHz in addition to 2 kHz. The default frequency for this output is 1.544 MHz (DS1). Programmable Synthesizer1 - Output Clock 1 (LVCMOS). This is a programmable clock output configurable as a multiple or division of the p1_clk0 frequency within the range of 2 kHz to 77.76 MHz. The default frequency for this output is 3.088 MHz (2x DS1). Feedback Clock (LVCMOS). This output is a buffered copy of the feedback clock for DPLL1. The frequency of this output always equals the frequency of the selected reference. DPLL2 Selected Output Reference (LVCMOS). This is a buffered copy of the output of the reference selector for DPLL2. Switching between input reference clocks at this output is not hitless. Differential Output Clock 0 (LVPECL). This output can be configured to provide any one of the available SDH clocks. The default frequency for this clock output is 155.52 MHz. Differential Output Clock 1 (LVPECL). This output can be configured to provide any one of the available SDH clocks. The default frequency for this clock output is 622.08 MHz clock. K10 p1_clk1 O H10 fb_clk O E1 dpll2_ref O A9 B10 A10 B9 Control H5 diff0_p diff0_n diff1_p diff1_n O O rst_b I Reset (LVCMOS, Schmitt Trigger). A logic low at this input resets the device. To ensure proper operation, the device must be reset after power-up. Reset should be asserted for a minimum of 300 ns. DPLL1 Hitless Switching Enable (LVCMOS, Schmitt Trigger). A logic high at this input enables hitless reference switching. A logic low disables hitless reference switching and re-aligns DPLL1's output phase to the phase of the selected reference input. This feature can also be controlled through software registers. This pin is internally pull up to Vdd. DPLL1 Mode Select 1:0 (LVCMOS, Schmitt Trigger). During reset, the levels on these pins determine the default mode of operation for DPLL1 (Automatic, Normal, Holdover or Freerun). After reset, the mode of operation can be controlled directly with these pins, or by accessing the dpll1_modesel register through the serial interface. This pin is internally pull up to Vdd. Differential Output 0 Enable (LVCMOS, Schmitt Trigger). When set high, the differential LVPECL output 0 driver is enabled. When set low, the differential driver is tristated reducing power consumption. This pin is internally pull up to Vdd. Differential Output 1 Enable (LVCMOS, Schmitt Trigger). When set high, the differential LVPECL output 1 driver is enabled. When set low, the differential driver is tristated reducing power consumption.This pin is internally pull up to Vdd. J5 dpll1_hs_en Iu C2 D2 dpll1_mod_sel0 dpll1_mod_sel1 Iu K1 diff0_en Iu D3 diff1_en Iu 7 Zarlink Semiconductor Inc. ZL30123 Pin # Status H1 dpll1_lock O Name I/O Type Description Data Sheet Lock Indicator (LVCMOS). This is the lock indicator pin for DPLL1. This output goes high when DPLL1's output is frequency and phase locked to the input reference. Holdover Indicator (LVCMOS). This pin goes high when DPLL1 enters the holdover mode. J1 dpll1_holdover O Serial Interface E2 F1 G1 E3 G2 sck si so cs_b int_b I I O Iu O Clock for Serial Interface (LVCMOS). Serial interface clock. Serial Interface Input (LVCMOS). Serial interface data input pin. Serial Interface Output (LVCMOS). Serial interface data output pin. Chip Select for Serial Interface (LVCMOS). Serial interface chip select. This pin is internally pull up to Vdd. Interrupt Pin (LVCMOS). Indicates a change of device status prompting the processor to read the enabled interrupt service registers (ISR). This pin is an open drain, active low and requires an external pull up to VDD. APLL Loop Filter A6 B6 C6 sdh_filter filter_ref0 filter_ref1 A A A External Analog PLL Loop Filter terminal. Analog PLL External Loop Filter Reference. Analog PLL External Loop Filter Reference. JTAG and Test J4 tdo O Test Serial Data Out (Output). JTAG serial data is output on this pin on the falling edge of tck. This pin is held in high impedance state when JTAG scan is not enabled. Test Serial Data In (Input). JTAG serial test instructions and data are shifted in on this pin. This pin is internally pull up to Vdd. If this pin is not used then it should be left unconnected. Test Reset (LVCMOS). Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin should be pulsed low on powerup to ensure that the device is in the normal functional state. This pin is internally pulled up to Vdd. If this pin is not used then it should be connected to GND. Test Clock (LVCMOS): Provides the clock to the JTAG test logic. If this pin is not used then it should be pulled down to GND. Test Mode Select (LVCMOS). JTAG signal that controls the state transitions of the TAP controller. This pin is internally pulled up to VDD. If this pin is not used then it should be left unconnected. K2 tdi Iu H4 trst_b Iu K3 J3 tck tms I Iu 8 Zarlink Semiconductor Inc. ZL30123 Pin # Name I/O Type Description Data Sheet Master Clock K4 osci I Oscillator Master Clock Input (LVCMOS). This input accepts a 20 MHz reference from a clock oscillator (TCXO, OCXO). The stability and accuracy of the clock at this input determines the free-run accuracy and the long term holdover stability of the output clocks. Oscillator Master Clock Output (LVCMOS). This pin must be left unconnected when the osci pin is connected to a clock oscillator. K5 osco O Miscellaneous B5 C5 D1 J2 J6 G3 K6 F2 F3 H7 NC IC IC IC IC IC IC IC IC IC No Connection. Leave unconnected. No Connection. Leave unconnected. No Connection. Leave unconnected. Internal Connection. Connect to ground. Internal Connection. Connect to ground. No Connection. Leave unconnected. Internal Connection. Leave unconnected. Internal Connection. Leave unconnected. Internal Connection. Leave unconnected. Internal Connection. Connect to ground. Power and Ground D9 E4 G8 G9 J8 J9 H6 H8 E8 F4 A5 A8 C10 B7 B8 H2 VDD P P P P P P P P P P P P P P P P Positive Supply Voltage. +3.3VDC nominal. VCORE AVDD Positive Supply Voltage. +1.8VDC nominal. Positive Analog Supply Voltage. +3.3VDC nominal. AVCORE Positive Analog Supply Voltage. +1.8VDC nominal. 9 Zarlink Semiconductor Inc. ZL30123 Pin # D4 D5 D6 D7 E5 E6 E7 F5 F6 F7 G4 G5 G6 G7 E9 F8 F9 H9 A7 C7 C8 C9 D8 H3 IId Iu OAPG- Data Sheet Description Name VSS I/O Type G G G G G G G G G G G G G G G G G G G G G G G G Ground. 0 Volts. AVSS Analog Ground. 0 Volts. Input Input, Internally pulled down Input, Internally pulled up Output Analog Power Ground 10 Zarlink Semiconductor Inc. ZL30123 1.0 Functional Description Data Sheet The ZL30123 SONET/SDH Line Card Synchronizer is a highly integrated device that provides timing and synchronization for network interface cards. It incorporates two independent DPLLs, each capable of locking to one of eight input references and provides a wide variety of synchronized output clocks and frame pulses. 1.1 DPLL Features The ZL30123 provides two independently controlled Digital Phase-Locked Loops (DPLL1, DPLL2) for clock and/or frame pulse synchronization. Table 1 lists the feature summary for both DPLLs. Feature Modes of Operation Loop Bandwidth Phase Slope Limiting Pull-in Range Reference Inputs Sync Inputs Input Ref Frequencies Supported Sync Input Frequencies Input Reference Selection/Switching Hitless Ref Switching Output Clocks DPLL1 Free-run, Normal (locked), Holdover User selectable: 14 Hz, 28 Hz, or wideband1 (890 Hz / 56 Hz / 14 Hz) User selectable: 885 ns/s, 7.5 s/s, 61 s/s, or unlimited Fixed: 130 ppm Ref0 to Ref7 Sync0, Sync1, Sync2 2 kHz, N * 8 kHz up to 77.76 MHz 166.67 Hz, 400 Hz, 1 kHz, 2 kHz, 8 kHz, 64 kHz. Automatic (based on programmable priority and revertiveness), or manual Can be enabled or disabled diff0_p/n, diff1_p/n, sdh_clk0, sdh_clk1, p0_clk0, p0_clk1, p1_clk0, p1_clk1, fb_clk. sdh_fp0, sdh_fp1, p0_fp0, p0_fp1 synchronized to active sync reference. As listed in Table 4 As listed in Table 4 DPLL2 Free-run, Normal (locked), Holdover. Fixed: 14 Hz User selectable: 61 s/s, or unlimited Fixed: 130 ppm Ref0 to Ref7 Sync inputs are not supported. 2 kHz, N * 8 kHz up to 77.76 MHz Sync inputs are not supported. Automatic (based on programmable priority and revertiveness), or manual Can be enabled or disabled p0_clk0, p0_clk1, p1_clk0, p1_clk1. Output Frame Pulses Supported Output Clock Frequencies Supported Output Frame Pulse Frequencies External Pins Status Indicators p0_fp0, p0_fp1 not aligned to sync reference. As listed in Table 4 for p0_clk0, p0_clk1, p1_clk0, p1_clk1 As listed in Table 4 for p0_fp0, p0_fp not aligned to sync reference. None Lock, Holdover Table 1 - DPLL1 and DPLL2 Features 1. In the wideband mode, the loop bandwidth depends on the frequency of the reference input. For reference frequencies equal to or greater than 64 kHz, the loop bandwidth = 890 Hz. For reference frequencies equal to or greater than 8 kHz and less than 64 kHz, the loop bandwidth = 56 Hz. For reference frequencies equal to 2 kHz, the loop bandwidth is equal to 14 Hz. 11 Zarlink Semiconductor Inc. ZL30123 1.2 DPLL Mode Control Data Sheet Both DPLL1 and DPLL2 independently support three modes of operation - free-run, normal and holdover. The mode of operation can be manually set or controlled by an automatic state machine as shown in Figure 2. All references are monitored for frequency accuracy and phase regularity, and at least one reference is qualified. Reset Free-Run Another reference is qualified and available for selection Lock Acquisition No references are qualified and available for selection Holdover Phase lock on the selected reference is achieved Selected reference fails Normal Normal (Locked) (Locked) Figure 2 - Automatic Mode State Machine Free-run The free-run mode occurs immediately after a reset cycle or when the DPLL has never been synchronized to a reference input. In this mode, the frequency accuracy of the output clocks is equal to the frequency accuracy of the external master oscillator. Lock Acquisition The input references are continuously monitored for frequency accuracy and phase regularity. If at least one of the input references is qualified by the reference monitors, then the DPLL will begin lock acquisition on that input. Given a stable reference input, the ZL30123 will enter in the Normal (locked) mode. Normal (locked) The usual mode of operation for the DPLL is the normal mode where the DPLL phase locks to a selected qualified reference input and generates output clocks and frame pulses with a frequency accuracy equal to the frequency accuracy of the reference input. While in the normal mode, the DPLL's clock and frame pulse outputs comply with the MTIE and TDEV wander generation specifications as described in Telcordia and ITU-T telecommunication standards. Holdover When the DPLL operating in the normal mode loses its reference input, and no other qualified references are available, it will enter the holdover mode and continue to generate output clocks based on historical frequency data collected while the DPLL was synchronized. 12 Zarlink Semiconductor Inc. ZL30123 1.3 Ref and Sync Inputs Data Sheet There are eight reference clock inputs (ref0 to ref7) available to both DPLL1 and DPLL2. The selected reference input is used to synchronize the output clocks. Each of the DPLLs have independent reference selectors which can be controlled using a built-in state machine or set in a manual mode. DPLL2 ref7:0 DPLL1 sync2:0 Figure 3 - Reference and Sync Inputs In addition to the reference inputs, DPLL1 has three optional frame pulse synchronization inputs (sync0 to sync2) used to align the output frame pulses. The syncn input is selected with its corresponding refn input, where n = 0, 1, or 2. Note that the sync input cannot be used to synchronize the DPLL, it only determines the alignment of the frame pulse outputs. An example of output frame pulse alignment is shown in Figure 4. Without a frame pulse signal at the sync input, the output frame pulses will align to any arbitrary cycle of its associated output clock. n = 0, 1, 2 x = 0, 1 refn syncn - no frame pulse signal present sdh/p0/p1_clkx sdh/p0_fpx When a frame pulse signal is present at the sync input, the DPLL will align the output frame pulses to the output clock edge that is aligned to the input frame pulse. n = 0, 1, 2 x = 0, 1 refn syncn sdh/p0/p1_clkx sdh/p0_fpx Figure 4 - Output Frame Pulse Alignment 13 Zarlink Semiconductor Inc. ZL30123 Data Sheet Each of the ref inputs accept a single-ended LVCMOS clock with a frequency ranging from 2 kHz to 77.76 MHz. Built-in frequency detection circuitry automatically determines the frequency of the reference if its frequency is within the set of pre-defined frequencies as shown in Table 2. Custom frequencies definable in multiples of 8 kHz are also available. 2 kHz 8 kHz 64 kHz 1.544 MHz 2.048 MHz 6.48 MHz 8.192 MHz 16.384 MHz 19.44 MHz 38.88 MHz 77.76 MHz Custom A Custom B Table 2 - Set of Pre-Defined Auto-Detect Clock Frequencies Each of the sync inputs accept a single-ended LVCMOS frame pulse. Since alignment is determined from the rising edge of the frame pulse, there is no duty cycle restriction on this input, but there is a minimum pulse width requirement of 5 ns. Frequency detection for the sync inputs is automatic for the supported frame pulse frequencies shown in Table 3. 166.67 Hz (48x 125 s frames) 400 Hz 1 kHz 2 kHz 8 kHz 64 kHz Table 3 - Set of Pre-Defined Auto-Detect Sync Frequencies 1.4 Ref and Sync Monitoring All input references (ref0 to ref7) are monitored for frequency accuracy and phase regularity. New references are qualified before they can be selected as a synchronization source, and qualified references are continuously monitored to ensure that they are suitable for synchronization. The process of qualifying a reference depends on four levels of monitoring. Single Cycle Monitor (SCM) The SCM block measures the period of each reference clock cycle to detect phase irregularities or a missing clock edge. In general, if the measured period deviates by more than 50% from the nominal period, then an SCM failure (scm_fail) is declared. 14 Zarlink Semiconductor Inc. ZL30123 Coarse Frequency Monitor (CFM) Data Sheet The CFM block monitors the reference frequency over a measurement period of 30 s so that it can quickly detect large changes in frequency. A CFM failure (cfm_fail) is triggered when the frequency has changed by more than 3% or approximately 30000 ppm. Precise Frequency Monitor (PFM) The PFM block measures the frequency accuracy of the reference over a 10 second interval. To ensure an accurate frequency measurement, the PFM measurement interval is re-initiated if phase or frequency irregularities are detected by the SCM or CFM. The PFM provides a level of hysteresis between the acceptance range and the rejection range to prevent a failure indication from toggling between valid and invalid for references that are on the edge of the acceptance range. When determining the frequency accuracy of the reference input, the PFM uses the external oscillator's output frequency (focsi) as its point of reference. Guard Soak Timer (GST) The GST block mimics the operation of an analog integrator by accumulating failure events from the CFM and the SCM blocks and applying a selectable rate of decay when no failures are detected. As shown in Figure 5, a GST failure (gst_fail) is triggered when the accumulated failures have reached the upper threshold during the disqualification observation window. When there are no CFM or SCM failures, the accumulator decrements until it reaches its lower threshold during the qualification window. CFM or SCM failures ref upper threshold lower threshold td gst_fail tq td - disqualification time tq - qualification time = n * td Figure 5 - Behaviour of the Guard Soak Timer during CFM or SCM Failures All sync inputs (sync0 to sync2) are continuously monitored to ensure that there is a correct number of reference clock cycles within the frame pulse period. 1.5 Output Clocks and Frame Pulses The ZL30123 offers a wide variety of outputs including two low-jitter differential LVPECL clocks (diff0_p/n, diff1_p/n), two SONET/SDH LVCMOS (sdh_clk0, sdh_clk1) output clocks and four programmable LVCMOS (p0_clk0, p0_clk1, p1_clk0, p1_clk1) output clocks. In addition to the clock outputs, two LVCMOS SONET/SDH frame pulse outputs (sdh_fp0, sdh_fp1) and two LVCMOS programmable frame pulses (p0_fp0, p0_fp1) are also available. 15 Zarlink Semiconductor Inc. ZL30123 Data Sheet The feedback clock (fb_clk) of DPLL1 is available as an output clock. Its output frequency is always equal to DPLL1's selected input frequency. The output clocks and frame pulses derived from the SONET/SDH APLL are always synchronous with DPLL1, and the clocks and frame pulses generated from the programmable synthesizers can be synchronized to either DPLL1 or DPLL2. This allows the ZL30123 to have two independent timing paths. P0 Synthesizer DPLL2 P1 Synthesizer p0_clk0 p0_fp0 p0_clk1 p0_fp1 p1_clk0 p1_clk1 diff0 DPLL1 SONET/SDH APLL diff1 sdh_clk0 sdh_fp0 sdh_clk1 sdh_fp1 Feedback Synthesizer fb_clk Figure 6 - Output Clock Configuration The supported frequencies for the output clocks and frame pulses are shown in Table 4. diff0_p/n, diff1_p/n (LVPECL) 6.48 MHz 19.44 MHz 38.88 MHz 51.84 MHz 77.76 MHz 155.52 MHz 311.04 MHz 622.08 MHz sdh_clk0, sdh_clk1 (LVCMOS) 6.48 MHz 9.72 MHz 12.96 MHz 19.44 MHz 25.92 MHz 38.88 MHz 51.84 MHz 77.76 MHz Table 4 - Output Clock and Frame Pulse Frequencies p0_clk0, p1_clk0 (LVCMOS) 2 kHz px_clk1 = N * 8 kHz (up to 77.76 MHz) p0_clk1, p1_clk1 (LVCMOS) px_clk0 2M sdh_fp0, shd_fp1, p0_fp0, p0_fp1 (LVCMOS) 166.67 Hz (48x 125 s frames) 400 Hz 1 kHz 2 kHz 4 kHz 8 kHz 32 kHz 64 kHz 16 Zarlink Semiconductor Inc. ZL30123 1.6 Configurable Input-to-Output and Output-to-Output Delays Data Sheet The ZL30123 allows programmable static delay compensation for controlling input-to-output and output-to-output delays of its clocks and frame pulses. All of the output synthesizers (SONET/SDH, P0, P1, Feedback) locked to DPLL1 can be configured to lead or lag the selected input reference clock using the DPLL1 Fine Delay. The delay is programmed in steps of 119.2 ps with a range of -128 to +127 steps giving a total delay adjustment in the range of -15.26 ns to +15.14 ns. Negative values delay the output clock, positive values advance the output clock. Synthesizers that are locked to DPLL2 are unaffected by this delay adjustment. In addition to the fine delay introduced in the DPLL1 path, the SONET/SDH, P0, and P1 synthesizers have the ability to add their own fine delay adjustments using the P0 Fine Delay, P1 Fine Delay, and SDH Fine Delay. These delays are also programmable in steps of 119.2 ps with a range of -128 to +127 steps. In addition to these delays, the single-ended output clocks of the SONET/SDH, P0, and P1 synthesizers can be independently offset by 90, 180 and 270 degrees using the Coarse Delay, and the SONET/SDH differential outputs can be independently delayed by -1.6 ns, 0 ns, +1.6 ns or +3.2 ns using the Diff Delay. The output frame pulses (SONET/SDH, P0) can be independently offset with respect to each other using the FP Delay. Coarse Delay P0 Synthesizer Coarse Delay FP Delay FP Delay Coarse Delay Coarse Delay p0_clk0 p0_clk1 p0_fp0 p0_fp1 p1_clk0 p1_clk1 diff0 diff1 sdh_clk0 sdh_clk1 sdh_fp0 sdh_fp1 fb_clk DPLL2 P0 Fine Delay P1 Fine Delay P1 Synthesizer Diff Delay Diff Delay DPLL1 SDH Fine Delay SONET/SDH APLL Coarse Delay Coarse Delay FP Delay FP Delay Feedback Synthesizer DPLL1 Fine Delay Figure 7 - Phase Delay Adjustments 17 Zarlink Semiconductor Inc. ZL30123 2.0 Software Configuration Data Sheet The ZL30123 is mainly controlled by accessing software registers through the serial peripheral interface (SPI). The device can be configured to operate in a highly automated manner which minimizes its interaction with the system's processor, or it can operate in a manual mode where the system processor controls most of the operation of the device. The following table provides a summary of the registers available for status updates and configuration of the device. . Addr (Hex) Register Name Reset Value (Hex) Description Type Miscellaneous Registers 00 01 id_reg use_hw_ctrl A7 00 Chip and version identification and reset ready indication register Allows some functions of the device to be controlled by hardware pins Interrupts 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F ref_fail_isr dpll1_isr dpll2_isr ref_mon_fail_0 ref_mon_fail_1 ref_mon_fail_2 ref_mon_fail_3 ref_fail_isr_mask dpll1_isr_mask dpll2_isr_mask ref_mon_fail_mask_0 ref_mon_fail_mask_1 ref_mon_fail_mask_2 ref_mon_fail_mask_3 FF 70 00 FF FF FF FF 00 00 00 FF FF FF FF Reference failure interrupt service register DPLL1 interrupt service register DPLL2 interrupt service register Ref0 and ref1 failure indications Ref2 and ref3 failure indications. Ref4 and ref5 failure indications Ref6 and ref7 failure indications Reference failure interrupt service register mask DPLL1 interrupt service register mask DPLL2 interrupt service register mask Control register to mask each failure indicator for ref0 and ref1 Control register to mask each failure indicator for ref2 and ref3 Control register to mask each failure indicator for ref4 and ref5 Control register to mask each failure indicator for ref6 and ref7 Reference Monitor Setup 10 11 detected_ref_0 detected_ref_1 FF FF Ref0 and ref1 auto-detected frequency value status register Ref2 and ref3 auto-detected frequency value status register R R R StickR StickR StickR StickR StickR StickR R/W R/W R/W R/W R/W R/W R/W R R/W Table 5 - Register Map 18 Zarlink Semiconductor Inc. ZL30123 Addr (Hex) 12 13 14 15 16 17 18 19 1A 1B 1C Register Name detected_ref_2 detected_ref_3 detected_sync_0 detected_sync_1 oor_ctrl_0 oor_ctrl_1 oor_ctrl_2 oor_ctrl_3 gst_mask_0 gst_mask_1 gst_qualif_time Reset Value (Hex) FF FF EE 0E 33 33 33 33 FF FF 1A Data Sheet Description Ref4 and ref5 auto-detected frequency value status register Ref6 and ref7 auto-detected frequency value status register Sync0 and sync1 auto-detected frequency value and sync failure status register Sync2 auto-detected frequency value and sync valid status register Control register for the ref0 and ref1 out of range limit Control register for the ref2 and ref3 out of range limit Control register for the ref4 and ref5 out of range limit Control register for the ref6 and ref7 out of range limit Control register to mask the inputs to the guard soak timer for ref0 to ref3 Control register to mask the inputs to the guard soak timer for ref4 to ref7 Control register for the guard_soak_timer qualification time and disqualification time for the references DPLL1 Control Type R R R R R/W R/W R/W R/W R/W R/W R/W 1D dpll1_ctrl_0 See Register Description See Register Description See Register Description 00 3C Control register for the DPLL1 filter control; phase slope limit, bandwidth and hitless switching Holdover update time, filter_out_en, freq_offset_en, revert enable Control register for the DPLL1 mode of operation DPLL1 reference selection or reference selection status Control register to mask each failure indicator (SCM, CFM, PFM and GST) used for automatic reference switching and automatic holdover Control register to indicate the time to restore a previous failed reference R/W 1E dpll1_ctrl_1 R/W 1F dpll1_modesel R/W 20 21 dpll1_refsel dpll1_ref_fail_mask R/W R/W 22 dpll1_wait_to_restore 00 R/W Table 5 - Register Map (continued) 19 Zarlink Semiconductor Inc. ZL30123 Addr (Hex) 23 24 25 26 27 28 29 Register Name dpll1_ref_rev_ctrl dpll1_ref_pri_ctrl_0 dpll1_ref_pri_ctrl_1 dpll1_ref_pri_ctrl_2 dpll1_ref_pri_ctrl_3 dpll1_lock_holdover_status reserved Reset Value (Hex) 00 10 32 54 76 04 03 Data Sheet Description Control register for the ref0 to ref7 enable revertive signals Control register for the ref0 and ref1 priority values Control register for the ref2 and ref3 priority values Control register for the ref4 and re5 priority values Control register for the ref6 and ref7 priority values DPLL1 lock and holdover status register Leave as default DPLL2 Control Type R/W R/W R/W R/W R/W R R/W 2A dpll2_ctrl_0 00 Control register to program the DPLL2: hitless switching, the phase slope limit and DPLL enable Control register to program the DPLL2: filter_out_en, freq_offset_en, revert enable Control register to select the mode of operation of the DPLL2 DPLL2 reference selection or reference selection status Control register to mask each failure indicator (SCM, CFM, PFM and GST) used for automatic reference switching and automatic holdover Control register to indicate the time to restore a previous failed reference for the DPLL2 path Control register for the ref0 to ref7 enable revertive signals Control register for the ref0 and ref1 priority values Control register for the ref2 and ref3 priority values Control register for the ref4 and re5 priority values Control register for the ref6 and ref7 priority values DPLL2 lock and holdover status register R/W 2B 2C 2D 2E dpll2_ctrl_1 dpll2_modesel dpll2_refsel dpll2_ref_fail_mask 04 02 00 3C R/W R/W R/W R/W 2F 30 31 32 33 34 35 dpll2_wait_to_restore dpll2_ref_rev_ctrl dpll2_ref_pri_ctrl_0 dpll2_ref_pri_ctrl_1 dpll2_ref_pri_ctrl_2 dpll2_ref_pri_ctrl_3 dpll2_lock_holdover_status 00 00 10 32 54 76 04 R/W R/W R/W R/W R/W R/W R P0 Configuration Registers Table 5 - Register Map (continued) 20 Zarlink Semiconductor Inc. ZL30123 Addr (Hex) 36 Register Name p0_enable Reset Value (Hex) 8F Data Sheet Description Control register to enable p0_clk0, p0_clk1, p0_fp0, p0_fp1, the P0 synthesizer and select the source Control register to generate p0_clk0, p0_clk1, p0_fp0 and p0_fp1 Control register for the [7:0] bits of the N of N*8k clk0 Control register for the [13:8] bits of the N of N*8k clk0 Control register for the p0_clk0 phase position coarse tuning Control register for the p0_clk1 frequency selection Control register for the p0_clk1 phase position coarse tuning Control register for the output/output phase alignment fine tuning for p0 path Control register to select the p0_fp0 frame pulse frequency Control register to select fp0 type Bits [7:0] of the programmable frame pulse phase offset in multiples of 1/262.14 MHz Bits [15:8] of the programmable frame pulse phase offset in multiples of 1/262.14 MHz Bits [21:16] of the programmable frame pulse phase offset in multiples of 8 kHz cycles Control register to select p0_fp1 frame pulse frequency Control register to select fp1 type Bits [7:0] of the programmable frame pulse phase offset in multiples of 1/262.144 MHz Bits [15:8] of the programmable frame pulse phase offset in multiples of 1/262.144 MHz Bits [21:16] of the programmable frame pulse phase offset in multiples of 8 kHz cycles Type R/W 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 p0_run p0_freq_0 p0_freq_1 p0_clk0_offset90 p0_clk1_div p0_clk1_offset90 p0_offset_fine p0_fp0_freq p0_fp0_type p0_fp0_offset_0 p0_fp0_offset_1 p0_fp0_offset_2 p0_fp1_freq p0_fp1_type p0_fp1_offset_0 p0_fp1_offset_1 p0_fp1_offset_2 0F 00 01 00 3E 00 00 05 83 00 00 00 05 11 00 00 00 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W P1 Configuration Registers 48 49 p1_enable p1_run 83 03 Control register to enable p1_clk0, p1_clk1, the P1 synthesizer and select the source Control register to generate enable/disable p1_clk0 and p1_clk1 R/W R/W Table 5 - Register Map (continued) 21 Zarlink Semiconductor Inc. ZL30123 Addr (Hex) 4A 4B 4C 4D 4E 4F Register Name p1_freq_0 p1_freq_1 p1_clk0_offset90 p1_clk1_div p1_clk1_offset90 p1_offset_fine Reset Value (Hex) C1 00 00 3F 00 00 Data Sheet Description Control register for the [7:0] bits of the N of N*8k clk0 Control register for the [13:8] bits of the N of N*8k clk0 Control register for the p1_clk0 phase position coarse tuning Control register for the p1_clk1 frequency selection Control register for the p1_clk1 phase position coarse tuning Control register for the output/output phase alignrment fine tuning Type R/W R/W R/W R/W R/W R/W SDH Configuration Registers 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D sdh_enable sdh_run sdh_clk_div sdh_clk0_offset90 sdh_clk1_offset90 sdh_offset_fine sdh_fp0_freq sdh_fp0_type sdh_fp0_offset_0 sdh_fp0_offset_1 sdh_fp0_offset_2 sdh_fp1_freq sdh_fp1_type sdh_fp1_offset_0 8F 0F 42 00 00 00 05 23 00 00 00 03 03 00 Control register to enable sdh_clk0, sdh_clk1, sdh_fp0, sdh_fp1 and the SDH PLL Control register to generate sdh_clk0, sdh_clk1, sdh_fp0 and sdh_fp1 Control register for the sdh_clk0 and sdh_clk1 frequency selection Control register for the sdh_clk0 phase position coarse tuning Control register for the sdh_clk1 phase position coarse tuning Control register for the output/output phase alignrment fine tuning for sdh path Control register to select the sdh_fp0 frame pulse frequency Control register to select fp0 type Bits [7:0] of the programmable frame pulse phase offset in multiples of 1/311.04 MHz Bits [15:8] of the programmable frame pulse phase offset in multiples of 1/311.04 MHz Bits [21:16] of the programmable frame pulse phase offset in multiples of 8 kHz cycles Control register to select sdh_fp1 frame pulse frequency Control register to select fp1 type Bits [7:0] of the programmable frame pulse phase offset in multiples of 1/311.04 MHz R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Table 5 - Register Map (continued) 22 Zarlink Semiconductor Inc. ZL30123 Addr (Hex) 5E 5F Register Name sdh_fp1_offset_1 sdh_fp1_offset_2 Reset Value (Hex) 00 00 Data Sheet Description Bits [15:8] of the programmable frame pulse phase offset in multiples of 1/311.04 MHz Bits [21:16] of the programmable frame pulse phase offset in multiples of 8 kHz cycles Type R/W R/W Differential Output Configuration 60 61 diff_ctrl diff_sel A3 53 Control register to enable diff0, diff1 and diffout1_high Control register to select the diff0 and diff1 frequencies R/W R/W External Feedback Configuration 62 63 64 65 66 67 fb_control fb_offset_fine reserved Custom Input Frequencies ref_freq_mode_0 ref_freq_mode_1 custA_mult_0 00 00 00 Control register to set whether to use auto detect, CustomA or CustomB for ref0 to ref3 Control register to set whether to use auto detect, CustomA or CustomB for ref4 to ref7 Control register for the [7:0] bits of the custom configuration A. This is the N integer for the N*8kHz reference monitoring. Control register for the [13:8] bits of the custom configuration A. This is the N integer for the N*8kHz reference monitoring. Control register for the custom configuration A: single cycle SCM low limiter Control register for the custom configuration A: single cycle SCM high limiter Control register for the custom configuration A: The [7:0] bits of the single cycle CFM low limit Control register for the custom configuration A: The [15:0] bits of the single cycle CFM low limit Control register for the custom configuration A: The [7:0] bits of the single cycle CFM high limit R/W R/W R/W 81 F5 Control register to enable fb_clk and the FB PLL, int/ext feedback select Control register for the output/output phase alignment fine tuning R/W R/W 68 custA_mult_1 00 R/W 69 6A 6B custA_scm_low custA_scm_high custA_cfm_low_0 00 00 00 R/W R/W R/W 6C custA_cfm_low_1 00 R/W 6D custA_cfm_hi_0 00 R/W Table 5 - Register Map (continued) 23 Zarlink Semiconductor Inc. ZL30123 Addr (Hex) 6E Register Name custA_cfm_hi_1 Reset Value (Hex) 00 Data Sheet Description Control register for the custom configuration A: The [15:0] bits of the single cycle CFM high limiter Control register for the custom configuration A: CFM reference monitoring cycles - 1 Control register for the custom configuration A: enable the use of ref_div4 for the CFM and PFM inputs Control register for the [7:0] bits of the custom configuration B. This is the 8 k integer for the N*8kHz reference monitoring. Control register for the [13:8] bits of the custom configuration B. This is the 8 k integer for the N*8kHz reference monitoring. Control register for the custom configuration B: single cycle SCM low limiter Control register for the custom configuration B: single cycle SCM high limiter Control register for the custom configuration B: The [7:0] bits of the single cycle CFM low limiter. Control register for the custom configuration B: The [15:0] bits of the single cycle CFM low limiter. Control register for the custom configuration B: The [7:0] bits of the single cycle CFM high limiter. Control register for the custom configuration B: The [15:0] bits of the single cycle CFM high limiter. Control register for the custom configuration B: CFM reference monitoring cycles - 1 Control register for the custom configuration B: enable the use of ref_div4 for the CFM and PFM inputs Type R/W 6F 70 custA_cfm_cycle custA_div 00 00 R/W R/W 71 custB_mult_0 00 R/W 72 custB_mult_1 00 R/W 73 74 75 custB_scm_low custB_scm_high custB_cfm_low_0 00 00 00 R/W R/W R/W 76 custB_cfm_low_1 00 R/W 77 custB_cfm_hi_0 00 R/W 78 custB_cfm_hi_1 00 R/W 79 7A custB_cfm_cycle custB_div 00 00 R/W R/W 7B 7F Reserved Table 5 - Register Map (continued) 24 Zarlink Semiconductor Inc. ZL30123 3.0 References Data Sheet AdvancedTCA, ATCA and the AdvancedTCA and ATCA logos are trademarks of the PCI Industrial Computer Manufacturers Group. This datasheet provides a summary of the high level features of the ZL30123. Refer to the ZL30123 Design Manual for a more complete description. 25 Zarlink Semiconductor Inc. For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request. Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE |
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